Espressif Systems /ESP32-S3 /SENSITIVE /CORE_1_PIF_PMS_CONSTRAIN_3

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Interpret as CORE_1_PIF_PMS_CONSTRAIN_3

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2 0CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3 0CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL 0CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1 0CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST 0CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CAN 0CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1 0CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1 0CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2 0CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT 0CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC 0CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR

Description

Core1 access peripherals permission configuration register 3.

Fields

CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2

Core1 access spi_2 permission in world0.

CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3

Core1 access spi_3 permission in world0.

CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL

Core1 access apb_ctrl permission in world0.

CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1

Core1 access i2c_ext1 permission in world0.

CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST

Core1 access sdio_host permission in world0.

CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CAN

Core1 access can permission in world0.

CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1

Core1 access pwm1 permission in world0.

CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1

Core1 access i2s1 permission in world0.

CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2

Core1 access uart2 permission in world0.

CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT

Core1 access rwbt permission in world0.

CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC

Core1 access wifimac permission in world0.

CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR

Core1 access pwr permission in world0.

Links

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